Master in Security of Integrated Systems and Application : Secure your future

Program

Integrated Circuits Test (17.5h)

Marie-Lise Flottes

Design of secure devices

  1. Introduction to integrated systems (7h)
  2. VHDL design (28h)
  3. VHDL synthesis (14h)
  4. Smart cards and silicon technologies (7h)
  5. Design of a cryptographic module (42h)
  6. Integrated circuits test (17.5h)
  7. Formal verification (17.5h)
  8. Embedded systems development (21h)
  9. Hardware security (7h)
  10. Side-channel analysis and counter-measures (28h)
  11. Fault analysis and counter-measures (17.5h)
  12. Bus security and integrated networks (3.5h)

Synopsis

This formation covers testing of analog and digital electronic systems with very large scale integration (VLSI). It gives essential data on test economics, classical semiconductor defects, simple test pattern coverage, structured design for testability techniques (scan, boundary scan, BIST) for system-on-a-chip design, automatic test equipment (constraints and costs), and selected advanced topics (IDDQ and delay faults testing, design for testability and secure systems).

Timetable

(A session amounts to 13/4 hours.)
Session 1
Introduction (Y. Bertrand)
Session 2
Fault modeling (Y. Bertrand)
Session 3
Automatic test pattern generation and fault simulation (C. Landrault)
Session 4
IDDQ and delay tests (P. Girard)
Session 5
Memory test (A. Virazel)
Sessions 6, 7 and 8
Design-for-testability [DFT] (P. Girard)
Session 9
Analog and mixed-signal test (M. Comte)
Session 10
DFT and secure designs (M.-L. Flottes)

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