English version    -  Ecrire  
 J.M. DUTERTRE

Research - Recherche                       

2008 - to present : Département Systèmes et Architectures Sécurisés [www] - ENMSE / CMP - GC

Publication list on HAL :  http://hal.archives-ouvertes.fr/aut/Jean-Max+DUTERTRE

Do not hesitate to ask for an author's version of any of the following research papers  

Journal papers 2018

Sensitivity to laser fault injection: CMOS FD-SOI vs. CMOS bulk,
J.-M. Dutertre, V. Beroulle, P. Candelier, S. D. Castro, L. Faber, M.-L. Flottes, P. Gendrier, D. Hély, R. Leveugle, P. Maistri, G. D. Natale, A. Papadimitriou, B. Rouzeyre
IEEE Transactions on Device and Materials Reliability, 2018 [www]   [pdf]

Assessing body built-in current sensors for detection of multiple transient faults
,
R. Viera, J.-M. Dutertre, M.-L. Flottes, O. Potin, G. D. Natale, B. Rouzeyre, and R. P. Bastos
 Microelectronics Reliability, 88- 90:128 – 134, 2018 [www]   [pdf]

Papers with proceedings 2018 :

Standard CAD Tool-Based Method for Simulation of Laser-Induced Faults in Large-Scale Circuits,
Raphael A.C. Viera, Jean-Max Dutertre, Philippe Maurine, and Rodrigo Possamai Bastos, ISPD 2018,
2018 International Symposium on Physical Design (ISPD '18)   [www] [talk]

The case of using CMOS FD-SOI rather than CMOS bulk to harden ICs against laser attacks,
J.-M. Dutertre, V. Beroulle, P. Candelier, L.-B. Faber, M.-L. Flottes, P. Gendrier, D. Hély, R. Leveugle, P. Maistri, G. Di Natale, A. Papadimitriou,  B. Rouzeyre, IOLTS 2018,
In On-Line Testing Symposium (IOLTS), 2018. [www] [talk]

Laser fault injection at the CMOS 28 nm technology node: an analysis of the fault model,
J.-M. Dutertre, V. Beroulle, P. Candelier, S. De Castro, L.-B. Faber, M.-L. Flottes, P. Gendrier, D. Hély, R. Leveugle, P. Maistri, G. Di Natale, A. Papadimitriou, B. Rouzeyre, FDTC 2018,
14th Workshop on Fault Diagnosis and Tolerance in Cryptography  [www] [talk]

Assessing Body Built-In Current Sensors for Detection of Multiple Transient Faults,
R. Viera, R. P. Bastos, J.-M. Dutertre, M.-L. Flottes, O. Potin, G. Di Natale, B. Rouzeyre, ESREF 2018,
29th European Symposium on Reliability of Electron Devices, Failure Physics and Analysis  [www] [talk]

Communications 2018 :

Targeting several unpipelined instructions with a single electromagnetic pulse on 8-bit microcontroller,
A. Menu, J.-L. Danger, J.-M. Dutertre, E. Kharbouche, O. Potin, and J.-B. Rigaud
16th International Workshops on Cryptographic architectures embedded in logic devices, CrytArchi 2018,  [www]

Experimental comparison and analysis of the sensitivity to laser fault injection of CMOS FD-SOI and CMOS bulk technologies
,
J.-M. Dutertre, PHISIC 2018
Workshop on Practical Hardware Innovations in Security Implementation and Characterization,  [www]

Laser Attacks against DDR Redundancy
,
P. Maistri, J.-M. Dutertre, R. Leveugle, SURREALIST 2018
Workshop on SecURity, REliAbiLity, test, prIvacy, Safety and Trust of Future Devices, 2018 - Bremen (Germany),  [www]   [talk]

Hardware attacks: theory and experimental state-of-the-art of laser fault injection attacks,
J.-M. Dutertre, PréGDR SécuInfo
Journées Nationales 2018 Pré-GDR Sécurité Informatique,  [www]   [talk]

Journal papers 2017

Method for evaluation of transient-fault detection techniques,
R. Viera, R. P. Bastos, J.-M. Dutertre, P. Maurine, R. I. Jadue, 
Microelectronics Reliability 76-77: 68-74 (2017) [www]   [pdf]

Papers with proceedings 2017

Role of Laser-Induced IR Drops in the Occurrence of Faults: Assessment and Simulation,
R. Viera, J.-M. Dutertre, R. P. Bastos, P. Maurine, DSD 2017,
 in: 2017 Euromicro Conference on Digital System Design (DSD)   [www]

Importance of IR drops on the modeling of laser-induced transient faults,
R. Viera, P. Maurine, J. M. Dutertre, R. P. Bastos, SMACD 2017,
14th Intl Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design  [www] [talk]

Communications 2017 :

A 45 minutes introduction to the practice and theory of laser fault injection,
J.-M. Dutertre, séminaire IRISA-INRIA
Séminaire sécurité des systèmes électroniques embarqués IRISA-INRIA,  [www]

Attaque par faute induisant un saut d'instruction
,
J.-M. Dutertre,
Rencontre Crypto'Puces 2017,  [www] 

L'enseignement de la sécurité à l'Ecole des Mines de Saint-Etienne,
Ph. Jaillon, J.-M. Dutertre,
27ème journée thématique sur la sécurité numérique,  [www] 

Journal papers 2016

Frontside Versus Backside Laser Injection: A Comparative Study,
S. De Castro, J.-M. Dutertre, B. Rouzeyre, G. Di Natale, M.-L. Flottes, 
ACM Journal on Emerging Technologies in Computing Systems (JETC) - Special Issue on Secure and Trustworthy Computing [www]

Book chapter 2016

Photonic Power Firewalls,
Dutertre,J.-M., Mirbaha A.-P., Naccache D., Tria A.
The New Codebreakers, 2016
Springer International Publishing,   [www]

Papers with proceedings 2016 :

Body Biasing Injection Attacks in Practice,
N. Beringuier-Boher, M. Lacruche, D. El-Baze, J.-M. Dutertre, J.-B. Rigaud, P. Maurine, CS2 2016,
Proceedings of the Third Workshop on Cryptography and Security in Computing Systems   [www] [talk]

On the Use of Forward Body Biasing to Decrease the Repeatability of Laser-Induced Faults,
M. Lacruche, N. Beringuier-Boher, J.-M. Dutertre, J.-B. Rigaud, E. Kussener, DATE 2016,
Design, Automation and Test in Europe Conference and Exhibition   [www] [talk]

Laser testing of a double-access bbics architecture with improved see detection capabilities
,
C. Champeix, J.-M. Dutertre, V. Pouget, B. Robisson, M. Lisart, N. Borrel, and A. Sarafianos, RADECS 2016,
Radiation Effects on Components and Systems workshop   [www] [talk]

Communications 2016 :

Assessment of the laser-induced fault model towards continuous CMOS technology shrinkage,
J.-M. Dutertre, et al., TRUDEVICE 2016
Workshop on Trustworthy Manufacturing and Utilization of Secure Devices, March 18th 2016, Dresden, Germany,  [www]   [pdf]

Practical results on laser-induced instruction-skip attacks into microcontrollers,
T. Riom, J.-M. Dutertre, O. Potin, J.-B. Rigaud, TRUDEVICE 2016
Workshop on Trustworthy Manufacturing and Utilization of Secure Devices, November 15th 2016, Barcelona, Spain,  [www]   [pdf]

Laser attacks on integrated circuits: assessment of the threat,
J.-M. Dutertre, et al., PHISIC 2016
Workshop on Practical Hardware Innovation in Security and Characterization, 3rd October 2016, Gardanne,  [www]   [pdf]

Journal papers 2015

Electrical model of an Inverter body biased structure in triple well technology under pulsed photoelectric laser stimulation,
N. Borrel, C. Champeix, E. Kussener, W. Rahajandraibe, M. Lisart, J.-M. Dutertre, A. Sarafianos,
Microelectronics Reliability, Volume 55, Issues 9-10, August-September 2015,   [www]

Book chapter 2015

Laser-Induced Fault Effects in Security-Dedicated Circuits,
V. Beroulle, P. Candelier, S. De Castro, G. Di Natale, J.-M. Dutertre, M.-L. Flottes, D. Hély, G. Hubert, R. Leveugle, et al.
VLSI-SoC: Internet of Things Foundations, 2015
Volume 464 of the series IFIP Advances in Information and Communication Technology pp 220-240,   [www]

Papers with proceedings 2015 :

Evaluation of Bulk Built-In Current Sensors Detecting Multiple Transient Faults,
R. A. Camponogara Viera, R. Possamai Bastos, J.-M. Dutertre, O. Potin, M.-L. Flottes, G. Di Natale, B. Rouzeyre, ATS 2015,
24th IEEE Asian Test Symposium, Mumbai India 2015

Electrical model of an Inverter body biased structure in triple well technology under pulsed photoelectric laser stimulation,
N. Borrel, C. Champeix, E. Kussener, W. Rahajandraibe, M. Lisart, J.-M. Dutertre, A. Sarafianos, ESREF 2015,
26th European Symposium on Reliability of Electron Devices, Failure Physics and Analysis   [www] [pdf]

Influence of triple-well technology on laser fault injection and laser sensor efficiency
,
N. Borrel, C. Champeix, E. Kussener, W. Rahajandraibe, M. Lisart, A. Sarafianos, J.-M. Dutertre, DFTS 2015
18th IEEE Symp. Defect and Fault Tolerance in VLSI and Nanotechnology Systems,  [www]   [pdf]

SEU sensitivity and modeling using pico-second pulsed laser stimulation of a D Flip-Flop in 40 nm CMOS technology,
C. Champeix, N. Borrel, J.-M. Dutertre, B. Robisson, M. Lisart, A. Sarafianos, DFTS 2015
18th IEEE Symp. Defect and Fault Tolerance in VLSI and Nanotechnology Systems,  [www]   [pdf]

Evidence of an information leakage between logically independent blocks,
L. Zussa, I. Exurville, J.-M. Dutertre, J.-B. Rigaud, B. Robisson, A. Tria, and J. Clédière, CS2 2015
Second Workshop on Cryptography and Security in Computing Systems   [www] [pdf]

Experimental validation of a Bulk Built-In Current Sensor for detecting laser-induced currents,
C. Champeix, N.Borrel, J.- M. Dutertre B. Robisson, M. Lisart, A. Sarafianos, IOLTS 2015
21st IEEE International On-Line Testing Symposium, July 6-8, 2015, Greece   [www] [pdf]

Laser Fault Injection into SRAM cells: Picosecond versus Nanosecond pulses,
M. Lacruche, N. Borrel, C. Champeix, J.-M. Dutertre, C. Roscian, A. Sarafianos, J.-B. Rigaud, E. Kussener, IOLTS 2015
21st IEEE International On-Line Testing Symposium, July 6-8, 2015, Greece   [www] [pdf]

Electrical Model of an NMOS Body Biased Structure in Triple-well Technology Under Photoelectric Laser Stimulation,
N. Borrel, C. Champeix, E. Kussener, W. Rahajandraibe, M. Lisart, J.-M. Dutertre and A. Sarafianos, IRPS 2015
IEEE International Reliability Physics Symposium, April 19-23, 2015, Monterey, CA, USA   [www] [pdf]

Figure of merits of 28nm Si technologies for imple- menting laser attack resistant security dedicated circuits,
S. De Castro, G. Di Natale, M.-L. Flottes, B. Rouzeyre, and J.-M. Dutertre, ISVLSI 2015
IEEE Computer Society Annual Symposium on VLSI, July 2015, Montpellier, France   [www] [pdf]

Communications 2015 :

Effets laser et fautes sur les circuits intégrés dédiés à la sécurité
J.-M. Dutertre, et al., Journée Sécurité Numérique du GDR SoC-SiP : 11ieme édition, 16 juin 2015, Télécom ParisTech,  [www]   [pdf]

Sensitivity to fault laser injection: a comparison between 28nm bulk and FD-SOI technology
S. De Castro, J.-M. Dutertre, G. Di Natale, M.-L. Flottes, B. Rouzeyre, TruDevice 2015,
TRUDEVICE 2015: Workshop on Trustworthy Manufacturing and Utilization of Secure Devices, March 13th 2015, Grenoble,  [www] [pdf]

Journal papers 2014

Improving the ability of Bulk Built-In Current Sensors to detect SEEs by using triple-well CMOS,
J.M. Dutertre, R. Possamai Bastos, O. Potin, M.L. Flottes,  B. Rouzeyre,  G. Di Natale, A. Sarafianos,
Microelectronics Reliability, Volume 54, Issues 9–10, September–October 2014,   [www] [pdf]

Papers with proceedings 2014 :

Efficiency of a Glitch Detector against Electromagnetic Fault Injection,
L. Zussa, A. Dehbaoui, K. Tobich, J.-M. Dutertre, P. Maurine, L. Guillaume-Sage, J. Clédiere, A. Tria, DATE 2014
Design Automation & Test in Europe,   [www] [pdf]

Analysis of the fault injection mechanism related to negative and positive power supply glitches using an on-chip voltmeter,
L. Zussa, J.-M. Dutertre, J. Clédiere, B. Robisson, HOST 2014
2014 IEEE Int. Symposium on Hardware-Oriented Security and Trust,   [www] [pdf]

Laser attacks on integrated circuits: from CMOS to FDSOI,    Invited paper
J.-M. Dutertre , S. De Castro, A. Sarafianos, N. Boher, B. Rouzeyre, M. Lisart, J. Damiens, P. Candelier, M.-L. Flottes and G. Di Natale, DTIS 2014,
9th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS),  [www] [pdf]

Improving the ability of Bulk Built-In Current Sensors to detect SEEs by using triple-well CMOS,
J.M. Dutertre, R. Possamai Bastos, O. Potin, M.L. Flottes, B. Rouzeyre, G. Di Natale, A. Sarafianos, ESREF 2014,
25th European Symposium on Reliability of Electron Devices, Failure Physics and Analysis   [www] [pdf]

Comparison of Bulk Built-In Current Sensors in terms of Transient-Fault Detection Sensitivity,
R. Possamai Bastos, F. Sill Torres, J.-M. Dutertre, VARI 2014,
5th European Workshop on CMOS Variability    [www] [pdf]

Laser-induced Fault Effects in Security-dedicated Circuits,     VLSI SoC 2014
R. Leveugle, P. Maistri, P. Vanhauwaert, F. Lu, G. Di Natale, M.-L. Flottes, B. Rouzeyre, A. Papadimitriou, D. Hely, V. Beroulle,
G. Hubert, S. De Castro, J.-M. Dutertre, A. Sarafianos, N. Boher, M. Lisart, J. Damiens, P. Candelier, C. Tavernier
22nd IFIP/IEEE International Conference on Very Large Scale Integration    [www]

ElectroMagnetic Analysis and Fault Injection onto Secure Circuits,     VLSI SoC 2014
P. Maistri, R. Leveugle, L. Bossuet, A. Aubert, V. Fischer, B. Robisson, N. Moro, P. Maurine, J.-M. Dutertre, M. Lisart,
22nd IFIP/IEEE International Conference on Very Large Scale Integration    [www] [pdf]

Characterization and simulation of a body biased structure in triple-well technology under pulsed photoelectric laser stimulation - Poster
N. Borrel, C. Champeix, E. Kussener, W. Rahajandraibe, M. Lisart, J-M. Dutertre, A. Sarafianos, ISTFA 2014
40th International Symposium for Testing and Failure Analysis   [www]  [pdf]

Evidence of a larger EM-induced fault model
S. Ordas, L. Guillaume-Sage, K. Tobich, J.-M.Dutertre, P. Maurine, Cardis 2014
13th Smart Card Research and Advanced Application Conference, France, November 5-7, 2014   [www]  [pdf]

Communications 2014 :

Analysis of a fault injection mechanism related to voltage glitches using an on-chip voltmeter
L. Zussa, J.-M. Dutertre, J. Clediere, B. Robisson, TRUDEVICE May 26-30 2014 ETS Workshop ,  [www]   [pdf]

Design of Bulk Built-In Current Sensors to Detect Single Event Effects and Laser-Induced Fault Injection Attempts - Poster
J.-M. Dutertre, R. Possamai Bastos, O. Potin, M.-L. Flottes, G. Di Natale, and B. Rouzeyre, Trudevice
Joint MEDIAN – TRUDEVICE Open Forum, September 30, 2014, Amsterdam (The Netherlands) ,  [www]   [pdf]

Journal papers 2013

Sensitivity tuning of a bulk built-in current sensor for optimal transient-fault detection,
J.M. Dutertre, R. Possamai Bastos, O. Potin, M.L. Flottes,  B. Rouzeyre,  G. Di Natale,
Microelectronics Reliability, Volume 53, Issues 9–11,   [www]   [pdf]

Electrical modeling of the photoelectric effect induced by a pulsed laser applied to an SRAM cell,
A. Sarafianos, C. Roscian, J.M. Dutertre, M. Lisart, A. Tria,
Microelectronics Reliability, Volume 53, Issues 9–11,   [www]   [pdf]

Papers with proceedings 2013 :

Building the electrical model of the pulsed photoelectric laser stimulation of an NMOS transistor in 90nm technology,
A. Sarafianos, O. Gagliano, M. Lisart, V. Serradeil, J.M. Dutertre, A. Tria, IRPS 2013
2013 IEEE International Reliability Physics Symposium (IRPS),   [www]   [pdf]

Electromagnetic Glitch on the AES Round Counter,
A. Dehbaoui, A.-P. Mirbaha, N. Moro, J.-M. Dutertre, A. Tria, Cosade 2013
Forth International Workshop on Constructive Side-Channel Analysis and Secure Design,   [www]   [pdf]

Frontside Laser Fault Injection on Cryptosystems - Application to the AES last round,
C. Roscian, J.-M. Dutertre, A. Tria,  HOST 2013
2013 IEEE Int. Symposium on Hardware-Oriented Security and Trust,   [www]   [pdf]

Power supply glitch induced faults: an in-depth analysis of the injection mechanism,
L. Zussa, J.-M.Dutertre, J. Clédière, A.Tria, IOLTS'13,
19th IEEE International On-Line Testing Symposium (IOLTS)  [www]   [pdf]

Sensitivity tuning of a bulk built-in current sensor for optimal transient-fault detection,
J.M. Dutertre, R. Possamai Bastos, O. Potin, M.L. Flottes,  B. Rouzeyre,  G. Di Natale, ESREF 2013,
24th European Symposium on Reliability of Electron Devices, Failure Physics and Analysis   [www] [pdf]

Electrical modeling of the photoelectric effect induced by a pulsed laser applied to an SRAM cell,
A. Sarafianos, C. Roscian, J.M. Dutertre, M. Lisart, A. Tria, ESREF 2013,
24th European Symposium on Reliability of Electron Devices, Failure Physics and Analysis   [www]  [pdf]

Fault Model Analysis of Laser-Induced Faults in SRAM Memory Cells,
C. Roscian, A. Sarafianos, J.-M. Dutertre, and A. Tria, FDTC 2013
10th Workshop on Fault Diagnosis and Tolerance in Cryptography,   [www]  [pdf]

Investigation of near-field pulsed EMI at IC level,
D. Amine, J.-M. Dutertre, B. Robisson, A. Tria, APEMC 2013
 Asia-Pacific International Symposium and Exhibition on Electromagnetic Compatibility : APEMC 2013,   [www]  [doi] 

Practical measurements of data path delays for IP authentification and integrity verification - Poster
I. Exurville, J. Fournier, J.-M. Dutertre, B. Robisson, and A. Tria, ReCoSoC 2013
8th International Workshop on Reconfigurable Communication-centric Systems-on-Chip,   [www]   [pdf]

Robustness improvement of an SRAM cell against laser-induced fault injection,
A. Sarafianos, C. Roscian, J.-M. Dutertre, M. Lisart, O. Gagliano, V. Serradeil and A. Tria, DFTS 2013
16th IEEE Symp. Defect and Fault Tolerance in VLSI and Nanotechnology Systems,   [www]   [pdf]

Differential Analysis of Round-Reduced AES Faulty Ciphertexts,
A.-P. Mirbaha, J.-M. Dutertre and A. Tria, DFTS 2013
16th IEEE Symp. Defect and Fault Tolerance in VLSI and Nanotechnology Systems,   [www]   [pdf]

A Single Built-in Sensor to Check Pull-up and Pull-down CMOS Networks against Transient Faults,
R. Possamai Bastos, F. Sill Torres, J.-M. Dutertre,  M.-L. Flottes, G. Di Natale, B. Rouzeyre, PATMOS 2013
23rd  International Workshop on Power and Timing Modeling, Optimization and Simulation,   [www]   [pdf]

Communications 2013 :

Discussion on the Model of Laser-Induced Faults in SRAM Memory Cells,
C. Roscian, A. Sarafianos, J.-M. Dutertre, A. Tria, M. Lisart, Cosade 2013
Forth International Workshop on Constructive Side-Channel Analysis and Secure Design,   [www]   [pdf]

From physical stresses to timing constraints violation,
L. Zussa, J.-M. Dutertre, J. Clédierre, A. Tria, Cosade 2013
Forth International Workshop on Constructive Side-Channel Analysis and Secure Design,   [www]   [pdf]

A Bulk Built-in Sensor for Detection of Fault Attacks - Poster
R. Possamai Bastos, F. Sill Torres, J.-M. Dutertre, M.-L. Flottes, G. Di Natale and B. Rouzeyre, HOST 2013,
2013 IEEE Int. Symposium on Hardware-Oriented Security and Trust,   [www]   [pdf]

The bad and the good of Physical functions,
B. Robisson, I. Exurville, J.-Y. Zie, H. Le Bouder, J.-M. Dutertre, J. Fournier, J.-B. Rigaud, CryptArchi 2013,
11th CryptArchi Workshop,   [www]   [pdf]

From physical stresses to timing constraints violation
L. Zussa, J.-M. Dutertre, J. Clédierre, A. Tria, Chip to Cloud 2013,
Chip-to-Cloud, Security Forum,   [www]   [pdf]

Laser-Induced Faults in SRAM Memory Cells: Experimental Results and Simulation-based Analysis
J.-M. Dutertre, C. Roscian, A. Sarafianos, M. Lacruche, TRUDEVICE Meeting 2013,  [www]   [pdf]

Journal papers 2012

Building the electrical model of the Photoelectric Laser Stimulation of a PMOS transistor in 90 nm technology,
A. Sarafianos, R. Llido, J.-M. Dutertre, O. Gagliano, V. Serradeil, M. Lisart, V. Goubier, A. Tria, V. Pouget, D. Lewis,
Microelectronics Reliability, Volume 52, Issues 9–10, September–October 2012,   [www]   [pdf]

Security Characterisation of a Hardened AES Cryptosystem Using a Laser,
C. Roscian, F. Praden, J.-M. Dutertre, J. Fournier, A. Tria,
TECHNICAL SCIENCES Abbrev.: Techn. Sc., No 15(1), Y 2012, ISSN 1505-4675,   [www]    [pdf]

Papers with proceedings 2012 :

Investigation of timing constraints violation as a fault injection means,
L. Zussa, J.-M. Dutertre, J. Clédière, B. Robisson and A. Tria, DCIS 2012
27th Conference on Design of Circuits and Integrated Systems (DCIS),   [www]   [paper]   [talk]

Electromagnetic Transient Faults Injection on a Hardware and Software Implementation of AES
,
A. Dehbaoui, J.-M. Dutertre, B. Robisson and A. Tria, FDTC 2012
9th Workshop on Fault Diagnosis and Tolerance in Cryptography,   [www]   [pdf]

A DFA on AES based on the Entropy of Error Distributions,
R. Lashermes, G. Reymond, J.-M. Dutertre, J. Fournier, B. Robisson and A. Tria, FDTC 2012
9th Workshop on Fault Diagnosis and Tolerance in Cryptography,   [www]   [pdf]

Fault Round Modification Analysis of the Advanced Encryption Standard,
J.-­M. Dutertre, A.-P. Mirbaha, D. Naccache, A.-L. Ribotta, A. Tria, T. Vaschalde, HOST 2012,
2012 IEEE Int. Symposium on Hardware-Oriented Security and Trust,   [www]   [pdf]

Characterization and TCAD simulation of 90 nm technology transistors under continuous photoelectric laser stimulation for failure analysis improvement
,
R. Llido, A. Sarafianos, O. Gagliano, V. Serradeil, V. Goubier, M. Lisart, G. Haller, V. Pouget, D. Lewis, J.M. Dutertre, A. Tria,
19th IEEE Int. Symposium on the Physical and Failure Analysis of Integrated Circuits - IPFA 2012   [www]
 
Characterization and TCAD simulation of 90 nm technology PMOS transistors under continuous photoelectric laser stimulation for failure analysis improvement,
R. Llido, A. Sarafianos, O. Gagliano, V. Serradeil, V. Goubier, M. Lisart, G. Haller, V. Pouget, D. Lewis, J.M. Dutertre, A. Tria, ISTFA 2012,
38th International Symposium for Testing and Failure Analysis   [www]

Building the electrical model of the Photoelectric Laser Stimulation of a PMOS transistor in 90nm technology,
A. Sarafianos, R. Llido, O. Gagliano, V. Serradeil, M. Lisart, V. Goubier, J.M. Dutertre, A. Tria, V. Pouget, D. Lewis, ESREF 2012,
23rd European Symposium on Reliability of Electron Devices, Failure Physics and Analysis   [www]   [pdf]

Building the electrical model of the Photoelectric Laser Stimulation of a NMOS transistor in 90nm technology,
A. Sarafianos, R. Llido, O. Gagliano, V. Serradeil, M. Lisart, V. Goubier, J.M. Dutertre, A. Tria, V. Pouget, D. Lewis, ISTFA 2012
38th International Symposium for Testing and Failure Analysis   [www] 

Communications 2012 :

A unified formalism for side-channel and fault attacks on cryptographic circuits,    Poster
B. Robisson, H. Lebouder, J.-M. Dutertre and A. Tria, DCIS 2012
27th Conference on Design of Circuits and Integrated Systems (DCIS),   [www]

Countermeasures against EM Analysis
,
P. Maistri, S. Tiran, A. Dehbaoui,P. Maurine, J.-M. Dutertre, CrypArchi 2012
10th International Workshops on Cryptographic Architectures Embedded in Reconfigurable Devices  [www] [pdf]

On the use of the EM medium as a fault injection means,
P. Maurine, A. Dehbaoui, F. Poucheret, J.-M. Dutertre, B. Robisson, A. Tria, , CrypArchi 2012
10th International Workshops on Cryptographic Architectures Embedded in Reconfigurable Devices  [www] [pdf]

Injection of transient faults using electromagnetic pulses -Practical results on a cryptographic system
A. Dehbaoui and J.M. Dutertre and B. Robisson and P. Orsatelli and P. Maurine and A. Tria
5th of march 2012, Cryptology ePrint Archive: Report 2012/123  [www]   [pdf]

Mise en œuvre d'une méthode de détection de « Trojans » matériels sur circuits AES.
I. Exurville, J. Fournier, J.-M. Dutertre
Journée Sécurité Numérique GDR SoC-SiP, ENST Paris 27 novembre 2012  [www]   [pdf]

Journal paper 2011

Design & characterisation of an AES chip embedding countermeasures,
Agoyan M., Bouquet S., Dutertre J.-M., Fournier J. J.-A, Rigaud J.-B., Robisson B.,Tria A., IJIEI 2011,
International Journal of Intelligent Engineering Informatics, special issue on "communication & security systems",  [www]

Papers with proceedings 2011 :

Review of fault injection mechanisms and consequences on countermeasures design,    Invited paper
Agoyan M., Dutertre J.-M., Mirbaha A.-P., Naccache D., Rigaud J.-B., Robisson B.,Tria A., DTIS 2011,
6th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS),  [www]   [pdf]

A Side-Channel and Fault-Attack Resistant AES Circuit Working on Duplicated Complemented Values,
Doulcier-Verdier M., Dutertre J.-M., Fournier J. J.-A., Rigaud J.-B., Robisson B., Tria A., ISSCC 2011,
2011 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC),  [www]   [pdf]

Design of a duplicated fault-detecting AES chip and yet using clock set-up time violations to extract 13 out of 16 bytes of the secret key,
M. Agoyan, S. Bouquet, M. Doulcier-Verdier, J.-M. Dutertre, J. Fournier, J.-B. Rigaud, B. Robisson, A.Tria, SSI 2011,
Smart System Integration, Dresden : Allemagne (2011),  [www]

Papers with proceedings 2010 :

Single-Bit DFA Using Multiple-Byte Laser Fault Injection,
Dutertre J.-M., Fournier J. J.-A., Mirbaha A.-P., Naccache D., Ribotta A.-L.,Tria A., HST 2010,
The tenth annual IEEE International Conference on Technologies for Homeland Security (IEEE HST '10) [www]

Reproducible single-byte laser fault injection,
J.-M. Dutertre, A.-P.MIRBAHA,  A.Tria, D.Naccache, PRIME'10,
6th IEEE Conference on Ph.D. Research in Microelectronics & Electronics (PRIME) [www]   [pdf]

How to flip a bit?
M.Agoyan, J.-M.Dutertre, A.-P.Mirbaha, D.Naccache, A.-L.Ribotta, A.Tria, IOLTS'10,
16th IEEE International On-Line Testing Symposium (IOLTS) [www]   [pdf]

Experimental Fault Injection around the Prototyping of an AES Cryptosystem,
Rigaud J.-B., Dutertre J.-M., Agoyan M., Robisson B., Tria A., ReCoSoC'10,
Reconfigurable Communication-centric Systems on Chip 2010 [www]   [pdf]

When Clocks Fail: On Critical Paths and Clock Faults
,
Agoyan M., Dutertre J.-M., Naccache D., Robisson B., Tria A., CARDIS 2010,
9th IFIP WG 8.1/11.2 International conference [www]    [pdf]

Communications 2010 :

Very Close to Perfect Solutions Against Power Attacks,
J.-M. Dutertre, A.-P. Mirbaha, D. Naccache, A. Tria,
Rump session Eurocrypt 2010 [www] [pdf]

Single-Byte Laser Faults Using Large Spots,
M. Agoyan, J.-M. Dutertre, A.-P. Mirbaha, D. Naccache, A.-L. Ribotta, A. Tria,
2nd PACA Security Trends in Embedded Security Workshop (PASTIS 2010) [pdf]

Revue expérimentale des techniques d'injection de fautes,
J.-M. Dutertre, A.-P. Mirbaha, A. Tria, B. Robisson, M. Agoyan,
Journée Sécurité Numérique GDR SoC-SiP, ENST Paris 31 mars 2010 [www] [pdf]

Communications 2009 :

Low cost fault injection method for security characterization,
Dutertre J.-M., Tria A., Robisson B., Agoyan M., e-Smart 2009 [www] [pdf]

Injection de fautes par modification de l'horloge : application à l'AES,
Dutertre J.-M., Tria A., Robisson B., Agoyan M., Crypto'puces 2009 [www] [pdf

2005 - 2008 : LaMIP - ENSICAEN

Joint laboratory NXP Semiconducteurs - ENSICAEN [www].

1999 - 2002 : LIRMM

PhD at LIRMM laboratory ( Laboratoire d'Informatique, de Robotique et de Microélectronique de Montpellier ).

Abstract
This thesis is devoted to the development of Single Event Upset hardness methodologies dedicated to SRAM based FPGA. SEU may alter the FPGA function through induced errors in the configuration memory. This is the major concern about the use of FPGA in radiation environment. Furthermore they affect the user logic in a similar way than classical integrated circuits.
Thanks to restructuration of their transistors arrangement and number, we propose a new inverter and data latch architectures. It allows us to define an SEU proof architecture for user logic hardness. This method is although applicable to harden the configuration memory.
However it is area consuming. So we propose a second methodology dedicated to the configuration memory. It is an Error Correction And Detection algorithm based on parity testing.
Finally we present the test circuit we designed to validate the restructurating approach.

Key-words:
Reconfigurable circuit, Robust design, FPGA, SRAM, Single Event Upset, EDAC,Radiation Hardness.

Résumé

Cette thèse est consacrée à l’étude de solutions de durcissement des circuits reconfigurables à base de SRAM aux effets radiatifs singuliers. Un partitionnement symbolique des FPGA en une couche de configuration et une couche opérative a permis de mettre en évidence et de hiérarchiser les erreurs d’origine radiative. C’est l’éventuelle inversion de bits de configuration qui est le principal facteur limitant l’usage des FPGA en milieu radiatif. Après avoir étudié les solutions actuellement retenues, nous présentons deux approches permettant d’assurer leur durcissement.
La première approche est basée sur la restructuration des inverseurs et des éléments de mémorisation au niveau de l’agencement de leurs transistors. Elle permet de durcir efficacement la couche opérative aux effets singuliers. Elle est également adaptée au durcissement de la couche de configuration, mais au prix d’un surcoût en surface important.
La deuxième approche repose sur l’utilisation d’un code détecteur et correcteur d’erreurs par test de la parité. Elle est dédiée au durcissement de la couche de configuration.
Un circuit test est également présenté afin de valider expérimentalement les principes de durcissement par restructuration que nous avons utilisés.

Mots-clés :
Circuits reconfigurables, FPGA, SRAM, Effets Singuliers, Durcissement aux radiations, Restructuration, Conception robuste.
Publications :
2002 - Thèse de doctorat : "Circuits Reconfigurables Robustes"  [pdf]
2001 - XVI  Conference on Design of Circuits and Integrated Systems
"Robustness of CMOS Circuits Designed for Space and Terrestrial Environment" :    [pdf]
2001 - IFIP International Conference on Very Large Scale Integration - System on Chip
"Integration of Robustness in the Design of a Cell" :    [pdf]
2001 - Conference on RADiation and its Effect on Components and systems - RADECS 2001
"Improving an SEU Hard Design using a Pulsed Laser" :    [www]