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 J.M. DUTERTRE

Research activities                       

From 2008 - Secure Systems and Architecture, research dpt. of ENMSE / CMP - GC [www] 

Papers list on HAL :  http://hal.archives-ouvertes.fr/aut/Jean-Max+DUTERTRE

Conference papers 2013 :

Electrical modeling of the photoelectric effect induced by a pulsed laser applied to an NMOS transistor,
A. Sarafianos, O. Gagliano, M. Lisart, V. Serradeil, J.M. Dutertre, A. Tria, IRPS 2013
2013 IEEE International Reliability Physics Symposium (IRPS),   [www]

Journal 2012

Building the electrical model of the Photoelectric Laser Stimulation of a PMOS transistor in 90 nm technology,
A. Sarafianos, R. Llido, J.-M. Dutertre, O. Gagliano, V. Serradeil, M. Lisart, V. Goubier, A. Tria, V. Pouget, D. Lewis,
In Press Microelectronic Reliability (2012), http://dx.doi.org/10.1016/j.microrel.2012.06.047,   [www]

Security Characterisation of a Hardened AES Cryptosystem Using a Laser,
C. Roscian, F. Praden, J.-M. Dutertre, J. Fournier, A. Tria,
TECHNICAL SCIENCES Abbrev.: Techn. Sc., No 15(1), Y 2012, ISSN 1505-4675,   [www] [pdf]

Conference papers 2012 :

Investigation of timing constraints violation as a fault injection means,
L. Zussa, J.-M. Dutertre, J. Clédière, B. Robisson and A. Tria, DCIS 2012
27th Conference on Design of Circuits and Integrated Systems (DCIS),   [www]

Electromagnetic Transient Faults Injection on a Hardware and Software Implementation of AES,
A. Dehbaoui, J.-M. Dutertre, B. Robisson and A. Tria, FDTC 2012
9th Workshop on Fault Diagnosis and Tolerance in Cryptography,   [www]

A DFA on AES based on the Entropy of Error Distributions,
R. Lashermes, G. Reymond, J.-M. Dutertre, J. Fournier, B. Robisson and A. Tria, FDTC 2012
9th Workshop on Fault Diagnosis and Tolerance in Cryptography,   [www]

Fault Round Modification Analysis of the Advanced Encryption Standard,
J.-­M. Dutertre, A.-P. Mirbaha, D. Naccache, A.-L. Ribotta, A. Tria, T. Vaschalde, HOST 2012,
2012 IEEE Int. Symposium on Hardware-Oriented Security and Trust,   [www]

Characterization and TCAD simulation of 90 nm technology transistors under continuous photoelectric laser stimulation for failure analysis improvement,
R. Llido, A. Sarafianos, O. Gagliano, V. Serradeil, V. Goubier, M. Lisart, G. Haller, V. Pouget, D. Lewis, J.M. Dutertre, A. Tria,
19th IEEE Int. Symposium on the Physical and Failure Analysis of Integrated Circuits - IPFA 2012   [www]
 
Characterization and TCAD simulation of 90 nm technology transistors under continuous photoelectric laser stimulation for failure analysis improvement,
R. Llido, A. Sarafianos, O. Gagliano, V. Serradeil, V. Goubier, M. Lisart, G. Haller, V. Pouget, D. Lewis, J.M. Dutertre, A. Tria, ISTFA 2012,
38th International Symposium for Testing and Failure Analysis   [www]

Building the electrical model of the Photoelectric Laser Stimulation of a PMOS transistor in 90nm technology,
A. Sarafianos, R. Llido, O. Gagliano, V. Serradeil, M. Lisart, V. Goubier, J.M. Dutertre, A. Tria, V. Pouget, D. Lewis, ESREF 2012,
23rd European Symposium on Reliability of Electron Devices, Failure Physics and Analysis   [www]

Building the electrical model of the Photoelectric Laser Stimulation of a NMOS transistor in 90nm technology,
A. Sarafianos, R. Llido, O. Gagliano, V. Serradeil, M. Lisart, V. Goubier, J.M. Dutertre, A. Tria, V. Pouget, D. Lewis, ISTFA 2012
38th International Symposium for Testing and Failure Analysis   [www]

Communications 2012 :

A unified formalism for side-channel and fault attacks on cryptographic circuits,    Poster
B. Robisson, H. Lebouder, J.-M. Dutertre and A. Tria, DCIS 2012
27th Conference on Design of Circuits and Integrated Systems (DCIS),   [www]

Countermeasures against EM Analysis,
P. Maistri, S. Tiran, A. Dehbaoui,P. Maurine, J.-M. Dutertre, CrypArchi 2012
10th International Workshops on Cryptographic Architectures Embedded in Reconfigurable Devices  [www] [pdf]

On the use of the EM medium as a fault injection means,
P. Maurine, A. Dehbaoui, F. Poucheret, J.-M. Dutertre, B. Robisson, A. Tria, , CrypArchi 2012
10th International Workshops on Cryptographic Architectures Embedded in Reconfigurable Devices  [www] [pdf]

Injection of transient faults using electromagnetic pulses -Practical results on a cryptographic system
A. Dehbaoui and J.M. Dutertre and B. Robisson and P. Orsatelli and P. Maurine and A. Tria
5th of march 2012, Cryptology ePrint Archive: Report 2012/123  [www] [pdf

Mise en œuvre d'une méthode de détection de « Trojans » matériels sur circuits AES.
I. Exurville, J. Fournier, J.-M. Dutertre
Journée Sécurité Numérique GDR SoC-SiP, ENST Paris 27 novembre 2012 [www] [pdf]

Journal 2011

Design & characterisation of an AES chip embedding countermeasures,
Agoyan M., Bouquet S., Dutertre J.-M., Fournier J. J.-A, Rigaud J.-B., Robisson B.,Tria A., IJIEI 2011,
International Journal of Intelligent Engineering Informatics, special issue on "communication & security systems",  [www]

Conference papers 2011 :

Review of fault injection mechanisms and consequences on countermeasures design,    Invited paper
Agoyan M., Dutertre J.-M., Mirbaha A.-P., Naccache D., Rigaud J.-B., Robisson B.,Tria A., DTIS 2011,
6th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS),  [www]

A Side-Channel and Fault-Attack Resistant AES Circuit Working on Duplicated Complemented Values,
Doulcier-Verdier M., Dutertre J.-M., Fournier J. J.-A., Rigaud J.-B., Robisson B., Tria A., ISSCC 2011,
2011 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC),  [www]

Design of a duplicated fault-detecting AES chip and yet using clock set-up time violations to extract 13 out of 16 bytes of the secret key,
M. Agoyan, S. Bouquet, M. Doulcier-Verdier, J.-M. Dutertre, J. Fournier, J.-B. Rigaud, B. Robisson, A.Tria, SSI 2011,
Smart System Integration, Dresden : Allemagne (2011),  [www]

Conference papers 2010 :

Single-Bit DFA Using Multiple-Byte Laser Fault Injection,
Dutertre J.-M., Fournier J. J.-A., Mirbaha A.-P., Naccache D., Ribotta A.-L.,Tria A., HST 2010,
The tenth annual IEEE International Conference on Technologies for Homeland Security (IEEE HST '10) [www]

Reproducible single-byte laser fault injection,
J.-M. Dutertre, A.-P.MIRBAHA,  A.Tria, D.Naccache, PRIME'10,
6th IEEE Conference on Ph.D. Research in Microelectronics & Electronics (PRIME) [www]

How to flip a bit?
M.Agoyan, J.-M.Dutertre, A.-P.Mirbaha, D.Naccache, A.-L.Ribotta, A.Tria, IOLTS'10,
16th IEEE International On-Line Testing Symposium (IOLTS) [www]

Experimental Fault Injection around the Prototyping of an AES Cryptosystem,
Rigaud J.-B., Dutertre J.-M., Agoyan M., Robisson B., Tria A., ReCoSoC'10,
Reconfigurable Communication-centric Systems on Chip 2010 [www]

When Clocks Fail: On Critical Paths and Clock Faults,
Agoyan M., Dutertre J.-M., Naccache D., Robisson B., Tria A., CARDIS 2010,
9th IFIP WG 8.1/11.2 International conference [www] 

Communications 2010 :

Very Close to Perfect Solutions Against Power Attacks,
J.-M. Dutertre, A.-P. Mirbaha, D. Naccache, A. Tria,
Rump session Eurocrypt 2010 [www] [pdf]

Single-Byte Laser Faults Using Large Spots,
M. Agoyan, J.-M. Dutertre, A.-P. Mirbaha, D. Naccache, A.-L. Ribotta, A. Tria,
2nd PACA Security Trends in Embedded Security Workshop (PASTIS 2010) [www] [pdf]

Revue expérimentale des techniques d'injection de fautes,
J.-M. Dutertre, A.-P. Mirbaha, A. Tria, B. Robisson, M. Agoyan,
Journée Sécurité Numérique GDR SoC-SiP, ENST Paris 31 mars 2010 [www] [pdf]

Communications 2009 :

Low cost fault injection method for security characterization,
Dutertre J.-M., Tria A., Robisson B., Agoyan M., e-Smart 2009 [www] [pdf]

Injection de fautes par modification de l'horloge : application à l'AES,
Dutertre J.-M., Tria A., Robisson B., Agoyan M., Crypto'puces 2009 [www] [pdf]

2005 - 2008 : LaMIP - ENSICAEN

Joint research team NXP Semiconducteurs - ENSICAEN.

1999 - 2002 : LIRMM

PhD at LIRMM laboratory ( Laboratoire d'Informatique, de Robotique et de Microélectronique de Montpellier ).

Abstract :
This thesis is devoted to the development of Single Event Upset hardness methodologies dedicated to SRAM based FPGA. SEU may alter the FPGA function through induced errors in the configuration memory. This is the major concern about the use of FPGA in radiation environment. Furthermore they affect the user logic in a similar way than classical integrated circuits.

Thanks to restructuration of their transistors arrangement and number, we propose a new inverter and data latch architectures. It allows us to define an SEU proof architecture for user logic hardness. This method is although applicable to harden the configuration memory. However it is area consuming.
So we propose a second methodology dedicated to the configuration memory. It is an Error Correction And Detection algorithm based on parity testing.
Finally we present the test circuit we designed to validate the restructurating approach.

Key words :
Reconfigurable circuit, Robust design, FPGA, SRAM, Single Event Upset, EDAC,Radiation Hardness.
Publications :
2002 - Thesis : "Circuits Reconfigurables Robustes"  [pdf]
2001 - XVI  Conference on Design of Circuits and Integrated Systems
"Robustness of CMOS Circuits Designed for Space and Terrestrial Environment" :    [pdf]
2001 - IFIP International Conference on Very Large Scale Integration - System on Chip
"Integration of Robustness in the Design of a Cell" :    [pdf]
2001 - Conference on RADiation and its Effect on Components and systems - RADECS 2001
"Improving an SEU Hard Design using a Pulsed Laser" :    [pdf]